A conventional memory testing device will be described with reference to FIGS. 4 through 7. A multi-port DRAM 2, which is a memory under test (hereinafter referred to as MUT), has a RAM part 2a and a SAM part 2b as shown in FIG. 4. The RAM part 2a has an address input terminal A, a control signal input terminal CT and a data I/O terminal D, whereas the SAM part 2b has a clock terminal CLK and a data I/O terminal D. Assuming, for the sake of simplicity, that the RAM part 2a has, for instance, 0 to 255 row addresses and 0 to 255 column addresses, that is, that M=N=255 in FIG. 4, a row address signal and a column address signal each have an 8-bit configuration.
(a) Test of RAM part
Timing signals, which are fed from main and sub timing generating parts 3a and 3b which form a timing generator 3, are supplied to main and sub pattern generating parts 4a and 4b which form a pattern generator 4. In synchronization with the input timing signal thereto, the main pattern generating part 4a responds to an instruction from an instruction memory, not shown, to generate and apply a control signal, a test pattern TP and an address signal MA for writing the test pattern to the RAM part 2a of the MUT 2. The address signal MA is fetched, as sets of row and column addresses (hereinafter referred to also as a main address), into the RAM part 2a and pattern data is written into or read out from memory cells selected by the main address. In general, a plurality of memory cells are provided at each address so that data of plural bits can be stored as one word, but one memory cell may also be provided. The data read out of the RAM part 2a is input into a main logical comparison part 6a, wherein it is compared with an expected pattern EP that is provided from the main pattern generating part 4a. Upon detecting a disagreement at any bit in the word read out from a certain address, a main failure signal MF=" 1" is immediately generated and fed to a main failure analysis memory 7a. The main failure analysis memory 7a has the same storage space as that of the RAM part 2a and is supplied at its address input terminal A with the same version as the main address signal MA that is applied to the RAM par 2a; hence, the main failure signal MF="1" is written into the memory 7a at the same address as that (a set of row and column addresses concerned) in the RAM part 2a where the word-containing the failure bit in the output from the SAM part 2b had been stored before it was transferred.
Thereafter, test patterns are sequentially written into the RAM part 2a at its all addresses and the same test as mentioned above is repeated; upon each occurrence of a failure bit, the main failure signal MF="1" is written into the main failure analysis memory 7a.
(b) Read/Transfer Test
A row address (hereinafter referred to as a transfer row address) of the RAM part 2a from which pieces of data are to be transferred to the SAM part 2b at one time is provided from the main pattern generating part 4a to the RAM part 2a; at the same time, a column address (hereinafter referred to as a SAM start address) that indicates the column address of the data transferred to the SAM part 2b at which serial read of the data is to start is provided to the SAM part 2b from the main pattern generating part 4a via the RAM part 2a. As shown in FIG. 6, the entire data at a row address transferred to the SAM part 2b is serially read out, starting at the specified column address (a SAM start address), and output on a word-by-word basis and input into a sub logical comparison part 6b for comparison with an expectation pattern input thereinto from the sub pattern generating part 4b. When a disagreement is detected between an arbitrary bit in the read-out word and the expected pattern, a sub failure signal SF="1" (SF="0" in the case of coincidence being detected) is immediately generated and input into a sub failure analysis memory 7b. The sub failure analysis memory 7b has the same storage capacity as that of the RAM part 2a. A sub address signal SA, which indicates the address (a set of row and column addresses) in the RAM part 2a where the data output from the SAM part 2b was stored prior to its transfer, is applied from the sub pattern generating part 4b to the sub failure analysis memory 7b, and the sub failure signal SF=1 is written into all memory cells at that address.
A program for generating from the sub pattern generating part 4b the sub address signal SA which is provided to the sub failure analysis memory 7b in the above read/transfer test is produced taking into account the address in the RAM part 2a where the data being read out of the SAM part 2b was stored. In this instance, the program must be generated taking into consideration of the main address signal MA (composed of the transfer row address and the SAM start address) from the main pattern generating part 4a--this poses a problem that the work-load for the generation of the program and its debug increases.
Incidentally, some of the latest multi-port DRAM's possess a split read/transfer function such that as shown in FIG. 7A, in the case of data transfer from the RAM part 2a to the SAM part 2b, the column address area of the SAM part 2b is divided at its center into two address areas (0 through 127 and 128 through 255, for instance), i.e. a lower address area SAM2b-L and an upper address area SAM2b-U and while one of them sequentially outputs pieces of data already transferred thereto from the corresponding column address area at transfer row addresses in the RAM part 2a, the other column address area receives data being transferred from the corresponding column address area at the transfer row addresses in the RAM part 2a, the two column address area alternating these operations. (The SAM during data output is called an active SAM and the other non-active SAM.) In this instance, start addresses S1 and S2 that are provided to the lower column address area SAM2b-L and the upper address area SAM2 b-U are supplied to the SAM part 2b from the main pattern generating part 4a via the RAM part 2a. The pieces of data transferred to the lower address area SAM2b-L are sequentially read out from the start address S1 to a lower-side maximum address AMI (=127) as indicated by the arrow in FIG. 7B, and in this white data is transferred from the RAM part 2a to the upper address area SAM2b-U. Next, the data thus transferred to the upper address area SAM2b-U is read out from the start address S2 to an upper-side maximum address AM 2 (=255) in such an order as indicated by the arrow in FIG. 7B.
Furthermore, some of the latest multi-port DRAM's have also a stop register control function that controls the split read/transfer by switching switches the destinationof data between the lower and upper address areas SAM2bL and SAM2b-U according to a set value (a stop address) in a built-in stop register (FIG. 7C). From the technical as well as work-load standpoints, it has become more and more difficult to program the sub address signal SA that is applied from the sub pattern generating part 4b to the sub failure analysis memory 7b, in combination with such a complex split read/transfer operation in these latest multi-port DRAM's.
It is therefore an object of the present invention to solve the problem of the prior art by a novel implementation of a sub address generator that is able to generate the sub address signal SA by hardware, not by software as in the prior art.